投币可乐-状态机( 二 ) _状态

<= IDLE;else case(state)IDLE:if (in_money == 2'b01)state <= HALF;else if (in_money == 2'b10)state <= ONE;elsestate <= IDLE;HALF: if (in_money == 2'b01)state <= ONE;else if (in_money == 2'b10)state <= ONE_HALF;elsestate <= HALF;ONE:if (in_money == 2'b01)state <= ONE_HALF;else if (in_money == 2'b10)state <= TWO;else state <= ONE;ONE_HALF:if (in_money == 2'b01)state <= TWO;else if (in_money == 2'b10)state <= IDLE;elsestate <= ONE_HALF;TWO :if (in_money == 2'b01 || in_money == 2'b10)state <= IDLE;else state <= TWO;default: state <= IDLE;endcasealways@(posedge sys_clk or negedge sys_rst_n)if (sys_rst_n == 0 )cola_out <= 1'b0;else if ((state == TWO && (in_money == 2'b01 || in_money == 2'b10) )|| (state == ONE_HALF && in_money == 2'b10))cola_out <= 1'b1;elsecola_out <= 1'b0;always@(posedge sys_clk or negedge sys_rst_n)if (sys_rst_n == 0 )out_money <= 1'b0;else if (state == TWO &&in_money == 2'b10 )out_money <= 1'b1;elseout_money <= 1'b0;endmodule
仿真代码与结果
`timescale 1ns / 1ns// Create Date: 2022/07/16 17:36:16module tb_complex_fsm();regsys_clk;regsys_rst_n ;regone; reghalf; wire out_money ; wire cola_out ; initial beginsys_clk = 1'b1;sys_rst_n <= 1'b0;#20sys_rst_n <= 1'b1;end//sys_clk:模拟系统时钟，每 10ns 电平翻转一次，周期为 20ns ，频率为 50MHzalways #10 sys_clk = ~sys_clk;//pi_money:产生输入随机数，模拟投币 1 元的情况always@(posedge sys_clk or negedge sys_rst_n)if(sys_rst_n == 1'b0){one, half} <= 2'b0;else{one, half} <= {$random} % 3; //取模求余数，产生非负随机数 0、1、2//------------------------complex_fsm_inst------------------------complex_fsm complex_fsm_inst(.sys_clk (sys_clk ), //input sys_clk.sys_rst_n (sys_rst_n ), //input sys_rst_n.one(one ), .half(half),.out_money (out_money),.cola_out (cola_out ) //output po_cola);endmodule
【投币可乐-状态机】结果：